Virtual Memory Fundamentals: Address Translation & Process Isolation

Definition
Virtual memory gives each process its own private address space. Addresses in your program are virtual. The CPU translates them to physical RAM locations. This provides isolation and lets the total virtual memory exceed physical RAM.
Address Translation Mechanics
The CPU divides virtual addresses into page number and offset. A 4 KB page uses 12 bits for offset, remaining bits for page number. The page table maps virtual page numbers to physical frame numbers. The MMU (Memory Management Unit) performs this translation on every memory access.
Page tables can be huge. A 48 bit virtual address space with 4 KB pages needs 2^36 entries. At 8 bytes each, that is 512 GB just for page tables. Multi level page tables solve this: only allocate table entries for memory regions actually used.
TLB: The Translation Cache
Page table lookups hit RAM. That would double memory latency if done for every access. The TLB (Translation Lookaside Buffer) caches recent translations. Modern CPUs have 64 to 1536 TLB entries. A TLB hit adds 1 cycle. A TLB miss triggers page table walk: 4 memory accesses for a 4 level table, roughly 200 nanoseconds.
TLB efficiency dominates memory performance for large working sets. With 4 KB pages and 1024 TLB entries, you cache 4 MB of address translations. Access patterns spanning more than 4 MB cause frequent TLB misses. Each miss costs 50x a hit. This is why huge pages matter for big data workloads.
Process Isolation Guarantees
Each process has its own page table. Virtual address 0x1000 in process A maps to different physical memory than 0x1000 in process B. A bug in one process cannot corrupt another's memory. The CPU enforces this in hardware. No software can bypass it without kernel privileges.
💡 Key Insight: Virtual memory abstracts physical memory like files abstract disk blocks. Programs use logical addresses; the OS and hardware map them to physical resources. This enables isolation, overcommit, and memory mapped files.

💡 Key Takeaways

✓Virtual addresses translate to physical through page tables; MMU does this on every access

✓TLB caches translations: 1 cycle hit vs 200ns miss for 4 level page walk

✓1024 TLB entries with 4 KB pages cache only 4 MB of translations

✓Multi level page tables avoid allocating entries for unused address ranges

✓Process isolation is hardware enforced: each process has separate page tables

📌 Interview Tips

1When asked about memory isolation, explain that each process has its own page table. Same virtual address maps to different physical memory

2Calculate TLB coverage: entries times page size. 1024 entries times 4 KB equals 4 MB. Explain why this matters for large working sets

3If discussing performance, mention TLB miss cost: 4 memory accesses for page table walk vs 1 cycle for hit

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